1. Field of the Invention
This invnention relates to computer systems and more particularly to power management units including internal configuration registers.
2. Description of the Relevant Art
Peripheral devices within computer systems typically include a plurality of so-called "configuration" registers. The configuration registers within a particular peripheral device are provided to store configuration data that controls user programmable operating parameters of the device. For example, configuration registers may be utilized within DMA (direct memory access) controllers to control the direction of a pending data transfer (i.e., memory-to-I/O or I/O-to-memory), the number of bytes to be transferred, and so on. Similarly, configuration registers may be utilized within timers to set programmable time periods and within interrupt controllers to set the priority and/or masking of various interrupt sources, among other things.
The configuration registers of a particular peripheral device are typically accessed by the host processor by first writing an offset value to an index register having a predetermined address within the I/O space. The offset value designates the particular configuration register being written or read. For example, an offset value comprised of 8-bits may be used to select any one of up to 256 different configuration registers. To actually write configuration data into the designated configuration register (pointed to by the off-set value of the index register), an I/O write cycle is executed to an address location referred to as the "configuration data register" location which is typically one word location beyond that of the index register. This causes the physical configuration register pointed to by the offset value of the index register to be written. Read operations to a designated configuration register are accomplished in a similar manner. By employing such an indexing technique, a plurality of configuration registers within the peripheral device may be selectively written or read while occupying, for example, only two word locations within the I/O addressable space of the computer system.
Power management units typically employ a plurality of configuration registers to control power management modes, time-out values, and the like. Within a typical system, the configuration registers of the power management unit are accessed by employing an indexing scheme similar to that described above. A problem results, however, if the index register address and the corresponding configuration data register address have I/O address values that conflict with the I/O mapping of other peripheral devices desired for employment within the computer system. If such a situation arises, either the power management unit or the conflicting peripheral device must be removed from the system. This limits the overall flexibility of the computer system.